The present invention is directed to testing semiconductor devices and, more particularly, to generating test patterns for detecting small delay defects in semiconductor processors.
Testing semiconductor processors during manufacture enables defects to be detected and is typically performed using automatic test equipment (ATE). Test patterns are usually generated by an automatic test pattern generator (ATPG). The test patterns are used to detect static defects, such as stuck-at defects and bridge defects.
Correct operation of the processor is often limited by timing considerations. Static timing analysis (STA) provides data that enables some analysis of simplified delay models and identification of some issues such as set-up and hold time violations, glitches, and clock skew, using definitions of critical paths and corners. The Device Under Test (DUT) can be tested in at-speed scan mode and in functional mode.
Delay testing commonly uses transition delay (TD) patterns created by ATPG tools to detect TD defects along selected paths of the DUT. However, TD patterns are inefficient in detecting a number of small delay defects (SDDs).
Small delay defects (SDD) are delays that are much smaller than the clock period. The accumulation of SDDs along critical paths with short timing slack may give an unacceptable failure rate of devices that are timing critical and subject to process variables caused by layout, mask production, and semiconductor processing variations, for example. The number of test patterns required to fully cover all fault locations of a complex processor is very high and the run time of such full test pattern generation is prohibitive.
The selection of limited numbers of paths and test patterns limits the run time of the test pattern generation. The paths targeted are selected with algorithms using fault models and static timing information (for example from a standard delay format (SDF) file). The selection of the paths suitable for SDD analysis is performed using the timing information interpreted by the tool. Due to the inaccurate interpretation of the delays, selection typically excludes a proportion of critical paths, and in addition TD patterns have not accurately targeted the critical paths for SDDs, particularly, leading to insufficient fault coverage.
Due to limitations in the timing analysis performed by the tools, and data not taken into account for some types of delay, the timing calculation and hence the selection of most suitable candidates targeted for SDD is inaccurate. Moreover, when the tool selects the path to target a particular node it may not be through the most critical path because of the inaccurate timing interpreted by the tool. The test pattern quality is then impacted twice in the process.
Thus, it would be advantageous to have a method for generating test patterns that detect SDDs better and that have acceptable run times.